The invention is directed to a method for accessing a common or shared memory of a multi-processor system composed of individual microprocessor systems, whereby the individual microprocessors access a common memory base region storing a common data base, with the use of appropriate matching devices, and with a multi-processor bus connected to all microprocessor systems, to allow a microprocessor system to access the common memory only for the duration of a system bus access cycle.
The User manual of the Mikroprozessor SAB 8086 (SAB 8086 Family, Users Manual, October 1979, MCS-86), Appendix AP 51 (A 113-A 131) discloses a multi-processor system wherein three identical microprocessor systems are connected with a common memory and a matching device for the connection of external equipment, via a multi-processor bus having control, address and data lines, and via signal carrying lines for the request and the allocation of the multi-processor bus. In each of the microprocessor systems, a local bus connects the individual system components such as microprocessor, and matching device to the data bus; and connects further devices such as, for example, local memory, etc. to one another. A bus control device is connected to, and is controlled by, the microprocessor to form the connecting element to the control bus. A multi-processor bus allocation device is also connected to the microprocessor, and to all bus allocation devices of the microprocessor system as well as to a priority device. Via the multi-processor bus allocation devices, and the priority device, the multi-processor bus is allocated to a given microprocessor for the duration of a multi-processor bus access cycle in a prescribed sequence, corresponding to the priority number allocated to each microprocessor system. A clock device allocated to each microprocessor system supplies the system components with the required clock information.
When such multi-processor systems are provided for the central controls of telecommunications switching systems, not only must the accesses to the multi-processor bus be coordinated but the accesses of the micro-processor systems to a data base stored in common for all in a corresponding region of the shared memory must also be controlled. Further, the access mode which serves for accesses onto the multi-processor bus which do not serve for up-dating or for reading the data base, dare not be influenced. Since information sets which belong together and are of different size are stored in the data base, a plurality of multi-processor bus accesses may be required for up-dating or reading out this information. Moreover, it must be assured that a read event is not carried out during the up-dating process and vice versa.